![]() ![]() ![]() The timing analysis is performed with HyperLynx and TimingDesigner.ġ. The FPGA static timing data is derived from SmartTime software. In this design example, a 32-bit CPU microprocessor core drives control signals to a 4-Mbit EEPROM multichip module (512 × 8-bit) interface device and Actel FPGA (Fig. Through WCTA, setup and hold time violations can be analyzed.Ī portion of an actual analysis is shown below as an example of the WCTA of an EEPROM interface. It usually accompanies many other assessments such as decoupling, signal integrity, and dc compatibility.įor WCTA, TimingDesigner analyzes the results of the printed-circuit board (PCB) propagation delay, extracted from HyperLynx and the static timing numbers of the FPGA or ASIC. The digital worst-case timing analysis (WCTA) portion of WCCA analyzes the timing of digital devices and signal paths under worst-case conditions. Worst-case circuit analysis is a cost-effective means of screening a design to verify with a high degree of confidence that potential defects and deficiencies are identified and eliminated prior to test, production, and delivery and that the design will function, within specifications, throughout its lifetime. ![]()
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